1. Technical Field
The embodiment relates to a mask for fabricating a semiconductor device, and more particularly to a method of forming a dummy pattern capable of reducing pattern density variation within a chip in a CMP (chemical mechanical polishing) process.
2. Background
By means of the reduction of a design rule according to high integration of a semiconductor device, for example, in technique below 0.18 μm there is a limitation to apply a LOCOS process thereto due to problems such as birds beak, etc., when forming a device isolating layer.
Therefore, in recent methods, a device isolating layer is formed by applying a shallow trench device isolation (STI) process where the birds beak does not occur.
The STI process generally consists of forming a trench in a device isolation area of a semiconductor substrate using a pad oxide film/a pad nitride film as a mask, burying the oxide film in the trench, and then planarizing it by means of a chemical mechanical polishing (CMP) process.
Such a CMP process sensitively reacts to pattern density so that it is important to maintain the pattern density within a chip to be constant. Therefore, it may be a key point to be designed in consideration of such a pattern density from the beginning of a design stage.
FIG. 1 is process cross-sectional view explaining a method of forming a device isolating layer using a dummy pattern in the related art, and FIG. 2 is a dummy rule used for forming the dummy pattern.
First, referring to FIG. 1, a pad oxide film 14b and a pad nitride film 14a are sequentially deposited on a semiconductor substrate 11. Then, a mask pattern 14 masking a portion of a relatively wide device isolation area is formed on the relatively wide device isolation area, where exposing a device isolation area of the substrate 11 by patterning the pad nitride film 14a and the pad oxide film 14b by means of a photolithography and an etching process.
Thereafter, a trench 16 is formed in the device isolation area by etching the substrate 11 using the mask pattern 14 and at the same time, a dummy pattern 17 is formed inside the trench 16 with a relatively wide width.
Herein, the dummy patter 17 is arranged spaced from the inner wall of the trench 16, and has a rectangular photo frame shape, wherein the both sides thereof have a straight profile.
Thereafter, an oxide film 15 is deposited over the substrate 11 so that the trench 16 is buried, and although not shown, the surface thereof is planarized by removing the oxide film 15 so that the surface of the mask pattern 14 is exposed by means of the CMP process and then the mask pattern 14 is removed so that a device isolating layer formed of the oxide film 15 is formed.
Referring to FIG. 2 for the dummy rule used in the related art, a dummy pattern 40 having the same pattern density is applied between the chip areas 20 and 30 where a plurality of devices are formed.
In other words, the chip areas 20 and 30 where the devices are formed are not formed having the same pattern density therebetween, but are generally formed so that the pattern density of the first chip area 20 is higher than that of the second chip area 30.
Therefore, as shown in the related art, when the dummy pattern 40 having the same pattern density is applied without considering the density difference of the chip areas 20 and 30 where the devices are formed, the variation of the pattern within the chip areas 20 and 30 is not reduced, causing the variation of the thickness of the polished surface in the subsequent CMP process.